The present disclosure relates to a method and to a device for programming at least one multi-level Phase Change Memory (PCM).
Phase change memory (PCM) is a non-volatile solid-state memory technology that exploits the reversible, thermally-assisted switching of specific chalcogenides between certain states of different electrical conductivity.
PCM is a promising and advanced emerging non-volatile memory technology mainly due to its excellent features including low latency, high endurance, long retention and high scalability. PCM may be considered a prime candidate for Flash replacement, embedded/hybrid memory and storage-class memory. Key requirements for competitiveness of PCM technology may be multilevel cell functionality, in particular for low cost per bit, and high-speed read/write operations, in particular for high bandwidth. Multilevel functionality, i.e. multiple bits per PCM cell, may be a way to increase capacity and thereby to reduce cost.
Multi-level PCM is based on storing multiple resistance levels between a lowest (SET) and a highest (RESET) resistance value. Multiple resistance levels or levels correspond to partial-amorphous and partial-crystalline phase distributions of the PCM cell. Phase transformation, i.e. memory programming, may be enabled by Joule heating. In this regard, Joule heating may be controlled by a programming current or voltage pulse. Storing multiple resistance levels in a PCM cell is a challenging task. Issues like process variability, as well as intra-cell and inter-cell material parameter variations may give rise to deviations of the achieved resistance levels from their intended values. One way to resolve this issue may be to resort to iterative programming schemes, in particular with multiple write-verify steps until a desired resistance level is reached.
In general, any iterative scheme aims to efficiently control the programming current through the cell in order to converge to the desired resistance level.
Several solutions have been proposed for multi-level PCM [1] and [2]. In [1], a programming scheme is presented that applies write pulses with amplitudes that are incrementally increased to approach the target resistance. In [2], a method is described that starts in the SET state, i.e. in the fully crystalline mode, and applies melting pulses to gradually amorphize the PCM cell.
When an access device, such as a field effect transistor (FET), is used to select a PCM cell in a cell-array, current control and iterative programming as such are achieved either by proper adjustment of the wordline (WL) voltage or the bitline (BL) voltage. In current memory architectures, WL-based programming is not preferred when it concerns high-bandwidth implementations. On the other hand, a main drawback of BL-based programming is that the current window, and equivalently the corresponding voltage window, for full-scale programming strongly depends on the threshold voltage barrier, especially when programming from a high to a low resistance state.
In the presence of cell variability, conventional WL-based programming and BL-based programming need a plurality of iterations to program cells in multiple states.